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文章背景与核心概要

现代芯片布局设计高度依赖于将半周长线长（HPWL）作为主要优化目标。然而，基准测试表明，HPWL与布线后时序指标（如最差负裕量 WNS 和总负现裕量 TNS）之间的相关性几乎为零，这导致现有的 AI 布局器在优化整体功耗、性能和面积（PPA）时，往往表现得不如标准的层次化基准。

为了克服这一挑战，作者推出了 PPAPlace——一种创新的时序驱动可微代理模型，旨在直接从宏模块（Macro）和标准单元布局中预测布线后的 PPA。通过利用全局布线后（post-global-routing）的标签以及双流神经网络架构，PPAPlace 将端到端的可微时序梯度反向传播至单元坐标中，从而在不损害功耗或布线性的前提下，显著改善布线后的时序性能。

PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

Authors: Ruogu Chen, Jie Han
Submitted: August 13, 2026
Primary Subject: Machine Learning (cs.LG) (Cross-listed: Artificial Intelligence, Hardware Architecture)
Accepted At: ICCAD 2026

📌 Executive Summary

Modern chip placement heavily relies on optimizing Half-Perimeter Wirelength (HPWL) as a primary objective. However, benchmarking reveals a near-zero correlation between HPWL and post-route timing metrics—such as Worst Negative Slack (WNS) and Total Negative Slack (TNS)—often causing existing AI placers to degrade overall Power, Performance, and Area (PPA) relative to standard hierarchical baselines.

To overcome this, the authors introduce PPAPlace, a novel timing-driven, differentiable surrogate model designed to predict post-route PPA directly from macro and standard-cell placements. By leveraging post-global-routing labels and dual-stream neural network architecture, PPAPlace injects end-to-end differentiable timing gradients back into cell coordinates to significantly improve post-route timing without compromising power or routability.

🔍 核心洞察与背景

  • The HPWL Disconnect: While traditional physical design tools prioritize wirelength minimization (HPWL), empirical studies show it has virtually no predictive power over final post-route timing (WNS and TNS).
  • AI Placer Degradation: Evaluation of existing artificial intelligence placers indicates performance degradation compared to traditional hierarchical baselines because they optimize proxy metrics unaligned with final circuit timing.
  • Label Fidelity Discovery: Evaluating various design flow stages demonstrates that post-global-routing yields the ideal balance between achieving high final timing fidelity and maintaining cost-effective label generation. Pre-route timing and macro-only representations are insufficient.

🛠️ 方法论：PPAPlace 的工作原理

PPAPlace 充当了一个双流可微代理预测器，弥合了跨阶段的优化目标：

PPAPlace serves as a dual-stream differentiable surrogate predictor that bridges cross-stage objectives:

  1. 双流架构：
  2. 结合了应用于芯片网表（netlist）的图注意力网络（GAT）以捕捉结构连接性。
  3. 在物理布局网格上利用空间卷积来捕捉空间布局依赖关系。
  1. Dual-Stream Architecture:
  2. Combines Graph Attention Networks (GAT) applied over the chip netlist to capture structural connectivity.
  3. Utilizes Spatial Convolutions over the physical placement grid to capture spatial layout dependencies.
  1. 全局布线后标签： 使用稳健的全局布线后标签进行训练，而不是不可靠的早期阶段估计。
  1. Post-Global-Routing Labels: Trained using robust post-global-routing labels rather than unreliable early-stage estimations.
  1. 端到端梯度流： 预测出的 WNS 和 TNS 梯度无缝地反向传播回到单元坐标。
  1. End-to-End Gradient Flow: Predicted WNS and TNS gradients propagate seamlessly back to cell coordinates.
  1. 优化策略：
  2. PPAPlace-CoOpt： 将预测的代理梯度作为协同目标直接注入到解析布局器（analytical placer）的优化循环中。
  3. PPAPlace-Refine： 作为布局后优化阶段运行，通过投影梯度下降法调整宏模块坐标。
  1. Optimization Strategies:
  2. PPAPlace-CoOpt: Injects the predicted surrogate gradients as a co-objective directly inside an analytical placer's optimization loop.
  3. PPAPlace-Refine: Operates as a post-placement refinement stage, adjusting macro coordinates via projected gradient descent.

📊 结果与性能

在五个从未见过的 ChiPBench 电路（完全从训练中排除，无需对测试电路进行重新训练）上进行测试，PPAPlace 实现了显著的性能提升：

Tested on five unseen ChiPBench circuits (excluded entirely from training without requiring test-circuit retraining), PPAPlace achieves substantial improvements:

  • 最差负裕量（WNS）相比层次化基准平均提升 22%。
  • 总负裕量（TNS）相比基准平均提升 51%。
  • PPA 保持： 在严格保持电路功耗和布线性不变的同时，成功改善了时序指标。
  • 22% average improvement in Worst Negative Slack (WNS) over the hierarchical baseline.
  • 51% average improvement in Total Negative Slack (TNS) over the baseline.
  • Preservation of PPA: Successfully enhances timing metrics while strictly maintaining circuit power consumption and routability.

🔗 资源与链接

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