文章背景与核心概要
随着智能体大语言模型(Agentic LLM)在模型上下文协议(MCP)上的广泛应用,在每一轮交互中重复编码冗长工具架构(schema)已成为制约性能的严重瓶颈,导致首字延迟(TTFT)大幅上升且内存开销居高不下。本文介绍的 Nexus 架构正是为解决这一痛点而设计的创新方案。
Nexus 采用双管齐下的技术路线:一方面通过检索解耦的路由机制实现高效的工具选择,另一方面利用深度自适应的 KV 缓存拼接技术进行上下文管理。在 Apple Silicon 统一内存架构下对 Qwen2.5-14B-Instruct 模型进行的测试表明,Nexus 在不牺牲输出保真度的前提下,实现了高达 1.7 倍的首字加速(TTFT)并大幅节省了 Token 消耗。
Nexus: Depth-Adaptive KV-Cache Splicing and Retrieval-Decoupled Tool Routing for Agentic LLMs on Unified Memory
arXiv: 2608.20397
Author: Mustafa Arslan
Submitted: July 1, 2026
Subject: Artificial Intelligence (cs.AI)
摘要
Nexus 是一个专为在模型上下文协议(MCP)上运行的智能体大语言模型(LLM)设计的创新架构。通过解决每一轮交互中重复编码冗长工具架构的瓶颈,Nexus 显著降低了首字延迟(TTFT)和内存开销。该系统采用双管齐下的方法:用于工具选择的检索解耦路由机制,以及用于上下文管理的深度自适应 KV 缓存拼接技术。在 Apple Silicon 统一内存上使用 Qwen2.5-14B-Instruct 模型进行测试时,Nexus 实现了高达 1.7 倍的 TTFT 加速以及显著的 Token 节省,同时未妥协输出保真度。
Summary Nexus is a novel architecture designed to optimize Agentic Large Language Models (LLMs) operating on the Model Context Protocol (MCP). By addressing the bottleneck of re-encoding verbose tool schemas during every turn, Nexus significantly reduces Time-to-First-Token (TTFT) and memory overhead. The system utilizes a dual-lever approach: a retrieval-decoupled routing mechanism for tool selection and a depth-adaptive KV-cache splicing technique for context management. Tested on the Qwen2.5-14B-Instruct model using Apple-silicon unified memory, Nexus achieves up to 1.7x faster TTFT and substantial token savings without compromising output fidelity.
核心创新
1. 检索解耦工具路由
随着工具注册表(registry)的不断增长,传统的智能体工作流会遭受二次方预填充(prefill)成本的困扰。Nexus 通过以下方式将路由与架构预填充解耦: * 语义旁路缓冲区(Semantic Lookaside Buffer, SLB): 利用带有校准交叉编码器边界门控的 INT8 缓冲区,通过检索来选择工具。 * 压缩签名(Compressed Signatures): 使用紧凑的文本签名(中位数为 19 个 Token)来生成参数,从而无需为每个工具处理完整的 KV 缓存。 * 效率: 即使工具注册表扩展到 250 个工具(在标准拼接下会导致上下文窗口溢出),仍能保持约 89% 的路由准确率。
1. Retrieval-Decoupled Tool Routing
Traditional agentic workflows suffer from quadratic prefill costs as tool registries grow. Nexus decouples routing from schema-prefill by: * Semantic Lookaside Buffer (SLB): Utilizing an INT8 buffer with a calibrated cross-encoder margin gate to select tools via retrieval. * Compressed Signatures: Arguments are generated using a compact textual signature (median 19 tokens), bypassing the need to process full KV caches for every tool. * Efficiency: Maintains ~89% routing accuracy even as the registry scales to 250 tools, where standard concatenation would otherwise overflow the context window.
2. 深度自适应 KV 缓存拼接
为了高效管理上下文,Nexus 将编译好的架构 KV 块直接移植到活跃上下文中。 * RoPE 保真度管理: 由于旋转位置嵌入(RoPE)的相位漂移会破坏注意力机制,Nexus 采用了“锚定拼接”(anchored splice)方法。 * 无缝修复: 对于超出阈值(\(P=256\))的放置,系统会触发深度自适应的后缀重新解码(redecode)。这确保了“永不退化”(never-regress)的特性,保证了输出保真度(top-1 一致性,\(D_{KL} \approx 0\))。
2. Depth-Adaptive KV-Cache Splicing
To manage context efficiently, Nexus transplants compiled schema KV blocks directly into the live context. * RoPE Fidelity Management: Because rotary position embedding (RoPE) phase drift can corrupt attention, Nexus employs an "anchored splice" method. * Seamless Repair: For placements beyond a threshold (\(P=256\)), the system triggers a depth-adaptive suffix redecode. This ensures a "never-regress" property, guaranteeing output fidelity (top-1 agreement, \(D_{KL} \approx 0\)).
性能亮点
- 延迟: 在中等深度下实现了 1.1–1.7 倍的 TTFT 加速。
- 资源使用: 主上下文 Token 消耗减少了约 80%。
- 鲁棒性: 该设计受限于两个关键发现:锚点外 RoPE 保真度边界,以及无参考漂移门控无法预测相位漂移(Spearman \(\rho = 0.193\))。
Performance Highlights
- Latency: Achieves a 1.1–1.7x TTFT speedup at moderate depths.
- Resource Usage: Reduces main-context token consumption by ~80%.
- Robustness: The design is bounded by two key findings: the off-anchor RoPE fidelity boundary and the inability of reference-free drift gates to predict phase drift (Spearman \(\rho = 0.193\)).
获取与资源
- 查看 PDF: arXiv:2608.20397
- HTML(实验性): arXiv HTML
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Access & Resources
- View PDF: arXiv:2608.20397
- HTML (Experimental): arXiv HTML
- License: Creative Commons Attribution 4.0
注:所有测量均基于 Apple Silicon 统一内存上的 Qwen2.5-14B-Instruct Q4_K_M 量化版本。虽然定量结果具有特定元组(tuple)的局限性,但定性架构边界旨在具备通用性。
Note: All measurements are based on the Qwen2.5-14B-Instruct Q4_K_M tuple on Apple-silicon unified memory. While quantitative results are tuple-specific, the qualitative architectural boundaries are intended to generalize.