跳转至

面向嵌入式系统早期原理图设计阶段的LLM驱动、数据表感知型自动化硬件兼容性验证

文章背景与核心概要

在嵌入式系统开发的早期（原理图设计之前），硬件组件之间的接口兼容性验证通常高度依赖人工查阅海量数据表（Datasheet），这不仅耗时费力，而且极易引入遗漏和错误。传统的“上传并提问（Upload-and-Query）”式大模型工作流由于上下文过长和缺乏结构化推理，难以胜任严谨的工程级数值和逻辑验证。

为此，本论文提出了一种全新的、基于大语言模型（LLM）驱动的硬件兼容性验证框架。该框架无需依赖详细的原理图仿真，而是直接利用组件数据表和高层连接描述，在文档级别识别接口不兼容问题。其核心创新在于采用“模块化任务分解”策略，通过构建设备连接的设计图谱、提取面向特定领域的工程属性，并生成确定性脚本来进行评估。这不仅彻底避免了让LLM直接进行易错的数值计算，还将输入上下文大小缩减了8.6倍，在包含34个数据表的7个嵌入式系统设计测试中实现了高达97.5%的兼容性验证准确率，展示了LLM在早期规范化硬件设计自动化中的巨大应用潜力。

📋 Summary

This paper introduces a novel, LLM-driven framework designed to verify hardware compatibility during the early, pre-schematic stages of embedded system design. By leveraging component datasheets and high-level connectivity descriptions rather than relying on detailed schematic simulations, the framework successfully identifies documentation-level interface incompatibilities.

Key innovations and findings include: * Modular Task Decomposition: Instead of directly querying large language models (LLMs) with raw documents, the framework constructs a design graph of device connectivity, extracts required engineering properties based on domain-oriented criteria, and generates deterministic scripts for evaluation. * Avoidance of LLM Computation: The LLM is used strictly for information transformation and script generation, completely avoiding error-prone numerical computations by the model. * High Performance: Tested across 7 embedded-system designs spanning 34 datasheets, the framework achieved a 97.5% compatibility-verification accuracy while reducing input context size by 8.6 times compared to conventional "upload-and-query" workflows.

📌 Article Metadata

  • arXiv ID: arXiv:2608.25217 [cs.AI]
  • Subjects: Artificial Intelligence (cs.AI); Systems and Control (eess.SY)
  • Authors: Haotian Qiao, Robert P. Dick
  • Submitted: August 25, 2026
  • DOI: 10.48550/arXiv.2608.25217

📄 Abstract

我们提出了一种由大语言模型驱动、具备数据表感知能力的早期硬件兼容性验证框架。该框架能够基于硬件数据表和高层组件连接描述，识别出文档层面的接口不兼容问题。它不需要（因此可以在）详细的原理图仿真和实现之前使用。我们将值得信赖的LLM辅助设计自动化视为：不是直接从文档中生成答案，而是通过可追溯的验证阶段来转换工程信息。给定硬件数据表和高层组件连接描述，该框架构建了一个能够捕获设备连接和共享交互域的设计图谱，仅检索显式、面向领域的验证准则所需的工程属性，并生成用于兼容性评估的确定性脚本。通过将兼容性分析分解为模块化阶段并保留中间结果，该框架减少了上下文开销、提高了透明度与可追溯性、增强了可扩展性，同时避免了依赖LLM进行数值计算。在包含34个数据表的七个嵌入式系统设计评估中，我们的框架实现了97.5%的兼容性验证准确率，与传统的“上传并提问”工作流相比，输入上下文大小减少了8.6倍。这些结果证明了在设计早期进行基于规范的LLM辅助硬件兼容性验证的可行性，以及模块化任务分解、形式化验证准则和任务感知紧凑上下文构建的必要性与显著优势。

We present an LLM-driven, datasheet-aware framework for early-stage hardware compatibility verification that identifies documentation-level interface incompatibilities based on hardware datasheets and high-level component connectivity descriptions. It does not require, and can therefore be used, before detailed schematic simulation and implementation. We view trustworthy LLM-assisted design automation not as directly generating answers from documents, but as transforming engineering information through traceable verification stages. Given hardware datasheets and high-level component connectivity descriptions, the framework constructs a design graph that captures device connectivity and shared interaction domains, retrieves only the engineering properties required by explicit, domain-oriented verification criteria, and generates deterministic scripts for compatibility evaluation. By decomposing compatibility analysis into modular stages and preserving intermediate results, the framework reduces context overhead, improves transparency and tractability, enables scaling, and avoids reliance on LLMs for numerical computation. Evaluated on seven embedded-system designs comprising 34 datasheets, our framework achieves 97.5% compatibility-verification accuracy and an 8.6 times reduction in input context size compared with "upload-and-query" workflows. These results demonstrate the feasibility of LLM-assisted, specification-based hardware compatibility verification at an early design stage, as well as the need for, and substantial benefits of, modular task decomposition, formalized verification criteria, and task-aware compact context construction.

🔗 Full-Text & Resources