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文章背景与核心概要

随着集成电路（IC）技术不断向纳米级微缩，传统的逻辑综合方法往往面临与物理设计严重脱节的问题。这种分离经常导致功耗、性能和面积（PPA）的恶化以及设计收敛周期的延长。传统的逻辑综合依赖于非物理的线负载模型（WLM），而较新的基于谱分析的布局预测器往往忽略了分层逻辑深度与信号流。

为了弥合这一鸿沟，本文推出了 LevelSyn——一个全新的物理感知逻辑综合框架，它将分层表示学习与线长驱动的优化引擎相结合。通过采用层异步图神经网络（GNN）以及层对齐的子图划分策略，LevelSyn 实现了高保真的门坐标预测和工业级规模的高效处理。作为集成到 Berkeley ABC 框架中的工具，LevelSyn 在 EPFL 基准测试集上展现出了显著的性能提升。

LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

Executive Summary

Executive Summary

As integrated circuit (IC) technology scales into the nanometer regime, traditional logic synthesis often suffers from a severe disconnect with physical design. This separation frequently results in Power, Performance, and Area (PPA) degradation and protracted design closure cycles. Conventional logic synthesis relies on non-physical Wire Load Models (WLMs), while newer spectral-based placement predictors often ignore hierarchical logic depth and signal flow.

As integrated circuit (IC) technology scales into the nanometer regime, traditional logic synthesis often suffers from a severe disconnect with physical design. This separation frequently results in Power, Performance, and Area (PPA) degradation and protracted design closure cycles. Conventional logic synthesis relies on non-physical Wire Load Models (WLMs), while newer spectral-based placement predictors often ignore hierarchical logic depth and signal flow.

To bridge this gap, this paper introduces LevelSyn, a novel physical-aware logic synthesis framework that pairs hierarchical representation learning with a wirelength-driven optimization engine. By using a level-asynchronous Graph Neural Network (GNN) and a level-aligned subgraph partitioning strategy, LevelSyn achieves high-fidelity gate coordinate prediction and efficient industrial-scale processing. Integrated into the Berkeley ABC framework, LevelSyn delivers remarkable performance improvements on the EPFL benchmark suite.

To bridge this gap, this paper introduces LevelSyn, a novel physical-aware logic synthesis framework that pairs hierarchical representation learning with a wirelength-driven optimization engine. By using a level-asynchronous Graph Neural Network (GNN) and a level-aligned subgraph partitioning strategy, LevelSyn achieves high-fidelity gate coordinate prediction and efficient industrial-scale processing. Integrated into the Berkeley ABC framework, LevelSyn delivers remarkable performance improvements on the EPFL benchmark suite.

Metadata & Publication Details

Metadata & Publication Details

  • Primary Subject: Hardware Architecture (cs.AR)
  • Primary Subject: Hardware Architecture (cs.AR)
  • Secondary Subjects: Artificial Intelligence (cs.AI), Machine Learning (cs.LG)
  • Secondary Subjects: Artificial Intelligence (cs.AI), Machine Learning (cs.LG)
  • Submission Date: September 3, 2026
  • Submission Date: September 3, 2026
  • Authors: Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu
  • Authors: Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu

Core Methodology

Core Methodology

  • Level-Asynchronous GNN: Captures the structural and directional semantics of And-Inverter Graphs (AIGs) to predict high-fidelity gate coordinates.
  • Level-Asynchronous GNN: Captures the structural and directional semantics of And-Inverter Graphs (AIGs) to predict high-fidelity gate coordinates.
  • Level-Aligned Subgraph Partitioning: Eliminates memory bottlenecks for industrial-scale designs while preserving local logical dependencies.
  • Level-Aligned Subgraph Partitioning: Eliminates memory bottlenecks for industrial-scale designs while preserving local logical dependencies.
  • Physics-Informed Synthesis Engine: Seamlessly integrates spatial insights into a newly developed module within the Berkeley ABC framework.
  • Physics-Informed Synthesis Engine: Seamlessly integrates spatial insights into a newly developed module within the Berkeley ABC framework.

Key Experimental Results

Key Experimental Results

Evaluated on the EPFL benchmark suite, LevelSyn achieves the following improvements over state-of-the-art (SOTA) methods:

Evaluated on the EPFL benchmark suite, LevelSyn achieves the following improvements over state-of-the-art (SOTA) methods:

  • Power Reduction: 6.89% average reduction.
  • Power Reduction: 6.89% average reduction.
  • Timing Delay Improvement: 27.48% enhancement.
  • Timing Delay Improvement: 27.48% enhancement.
  • Design Rule Check (DRC) Validation: 99.59% reduction in DRC violations post-place-and-route, effectively accelerating design convergence.
  • Design Rule Check (DRC) Validation: 99.59% reduction in DRC violations post-place-and-route, effectively accelerating design convergence.